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19-1674; Rev 0; 4/00
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
General Description
The MAX5168 contains 32 sample/hold amplifiers and four 1-of-8 multiplexers. The logic controlling the muxes and sample/hold amplifiers combines the four muxes into a unified 1-of-32 multiplexer with a sample/hold at each output. Additional logic allows two devices to function as a single 64-channel unit. The MAX5168 is available with an output impedance of 50, 500, or 1k. The MAX5168 operates with +10V and -5V supplies, and a separate +5V digital logic supply. Manufactured with a proprietary BiCMOS process, it provides high accuracy, fast acquisition time, a low droop rate, and a low hold step. The MAX5168 has a typical linearity error of less than 0.01% and can accurately acquire 8V step input signals to 0.01% accuracy in 2.5s within the +7V to -4V input signal range. Transitions from sample mode to hold mode result in only a 0.5mV error. While in hold mode, the output voltage slowly droops at a rate of 1mV/s. The MAX5168 is available in a 48-pin TQFP package and is specified for both the commercial (0C to +70C) and extended industrial (-40C to +85C) temperature ranges. o 32-Channel Sample/Hold o 0.01% Accuracy of Acquired Signal o 0.01% Linearity Error o Fast Acquisition Time: 2.5s o Low Droop Rate: 1mV/s o Low Hold Step: 0.25mV o Wide Output Voltage Range: +7V to -4V
Features
MAX5168
Ordering Information
PART MAX5168LCCM MAX5168MCCM MAX5168NCCM MAX5168LECM MAX5168MECM MAX5168NECM TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP ROUT () 50 500 1k 50 500 1k
________________________Applications
Automatic Test Systems (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment
ADDR2 ADDR3 ADDR4 SELECT S/H CONFIG VL DGND VSS AGND IN N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin Configuration
TOP VIEW
ADDR1 ADDR0 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25 18 19 20 21 22 23 24
OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 VDD OUT15 OUT14 OUT13 OUT12 OUT11
MAX5168
________________________________________________________________ Maxim Integrated Products
N.C. OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10
TQFP
1
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +11.0V VSS to AGND .........................................................-6.0V to +0.3V VDD to VSS ......................................................................+15.75V VL to DGND ...........................................................-0.3V to +6.0V VL to AGND ...........................................................-0.3V to +6.0V DGND to AGND.....................................................-0.3V to +2.0V IN, OUT_ .....................................................................VSS to VDD Logic Inputs to DGND ...........................................-0.3V to +6.0V Maximum Current into OUT_ ............................................10mA Maximum Current into Logic Inputs .................................20mA Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 12.5mW/C above +70C)......1000mW Operating Temperature Ranges MAX5168_CCM ................................................0C to +70C MAX5168_ECM..............................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10.0V, VSS = -5.0V, VL = +5.0V 5%, AGND = DGND = 0, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG SECTION Linearity Error Hold Step Droop Rate Offset Voltage Output Voltage Range VOS VOUT_ VHS -4.0V < VIN < +7V, RL = IN = AGND IN = AGND, TA = +25C IN = AGND, TA = +25C +15C TA +65C (Note 1) RL = CL = 250pF for MAX5168L CL = 10nF for MAX5168M/N MAX5168L MAX5168M MAX5168N VSS + 0.75 -72 -72 -76 dB -76 10 35 350 700 2 2 VSS TA = +25C, RL = , Figure 2 Figure 2 (Note 1) 8V step to 0.08% 100mV step to 1mV 2.5 1 1 2 200 VDD 4 50 500 1000 20 65 650 1300 mA mA V pF -30 0.01 0.25 1 -5 20 0.08 1.00 40 +30 40 VDD 2.4 % mV mV/s mV V/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
Analog Crosstalk
8V step with 500ns rising edge (Note 1) CIN ROUT_ ISOURCE ISINK VCH (Note 1) RL = , CL = 250pF VIN = 0, sample mode VIN = 0, sample mode
Input Capacitance DC Output Impedance Output Source Current Output Sink Current Output Clamp High TIMING PERFORMANCE Acquisition Time Hold-Mode Settling Time Aperture Delay
tAQ tH tAP
s s ns
To 1mV of final value, Figure 2 (Note 1)
2
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10.0V, VSS = -5.0V, VL = +5.0V 5%, AGND = DGND = 0, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER S/H Pulse Width Data Setup Time Data Hold Time DIGITAL INPUTS Input Voltage High Input Voltage Low Input Current POWER SUPPLIES Positive Analog Supply Negative Analog Supply Digital Logic Supply Positive Analog Supply Current Negative Analog Supply Current VDD VSS VL IDD ISS RL = RL = ADDR_ = DGND or VL, S/H = DGND or VL ADDR_ = 0.8V or 2.0V, S/H = 0.8V or 2.0V For VDD and VSS, sample mode, IN = AGND -60 -75 (Note 2) (Note 2) 9.5 -4.75 4.75 10 -5 5 10.5 -5.45 5.25 36 36 0.5 5 V V V mA mA mA mA dB VIH VIL II IN = DGND or VCC -1 2.0 0.8 +1 V V A SYMBOL tPW tSET tDH CONDITIONS Figure 2 (Note 1) Figure 2 (Note 1) Figure 2 (Note 1) MIN 200 50 150 TYP MAX UNITS ns ns ns
MAX5168
Digital Logic Supply Current
IL
Power-Supply Rejection Ratio
PSRR
Note 1: Guaranteed by design. Note 2: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
Typical Operating Characteristics
(VDD = +10V, VSS = -5V, VL = +5V, VIN = +5V, RL = , CL = 0, AGND = DGND = 0, VCH = VDD, VCL = VSS, TA = +25C, unless otherwise noted.)
DROOP RATE vs. INPUT VOLTAGE
MAX5168 TOC 01
DROOP RATE vs. TEMPERATURE
MAX5168 TOC 02
POWER-SUPPLY REJECTION RATIO SAMPLE MODE
NEGATIVE SUPPLY (VSS) -100 POSITIVE SUPPLY (VDD) -80 PSRR (dB)
MAX5168 TOC 03
2.0 1.8 1.6 DROOP RATE (mV/s) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -4 -3 -2 -1 0 1 2 3 4 5 6 7 INPUT VOLTAGE (V)
50
-120
40 DROOP RATE (mV/s)
30
-60 -40
20
10
-20 0 -40 -15 10 35 60 85 0.1 1 10 100 1000 10,000 TEMPERATURE (C) FREQUENCY (kHz)
0
POWER-SUPPLY REJECTION RATIO HOLD MODE
POSITIVE SUPPLY (VDD) -100 -80 PSRR (dB) NEGATIVE SUPPLY (VSS) -60 -40 -20 0 0.1 1 10 100 1000 10,000 FREQUENCY (kHz)
MAX5168 TOC 04
HOLD STEP vs. INPUT VOLTAGE
MAX5168 TOC 05
HOLD STEP vs. TEMPERATURE
115 110 HOLD STEP (V) 105 100 95 90 85 80
MAX5168 TOC 06
-120
-160 -140 -120 HOLD STEP (V) -100 -80 -60 -40 -20 0 -4 -3 -2 -1 0 1 2 3 4 5 6 7 INPUT VOLTAGE (V)
120
-55
-35
-15
5
25
45
65
85
TEMPERATURE (C)
OFFSET VOLTAGE vs. INPUT VOLTAGE
MAX5168 TOC 07
OFFSET VOLTAGE vs. TEMPERATURE
MAX5168 TOC 08
-3.0 -3.2 -3.4 OFFSET VOLTAGE (mV) -3.6 -3.8 -4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -4 -3 -2 -1 0 1 2 3 4 5 6 7 INPUT VOLTAGE (V)
0 -1 OFFSET VOLTAGE (mV) -2 -3 -4 -5 -6 -7 -40 -15 10 35 60
85
TEMPERATURE (C)
4
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12, 13 14-29 30 31-46 47 48 NAME ADDR2 ADDR3 ADDR4 SELECT S/H CONFIG VL DGND VSS AGND IN N.C. OUT0-OUT15 VDD OUT16-OUT31 ADDR0 ADDR1 Bit 2 of the Address Decoder Bit 3 of the Address Decoder Bit 4 of the Address Decoder Enables the S/H pin. The polarity of SELECT is determined by the state of the CONFIG pin. If CONFIG is low, then SELECT is active-high. If CONFIG is high, then SELECT is active-low. When SELECT is not in its active state, all 32 channels are in hold mode independent of the S/H pin. Puts the selected channel into sample mode when low. Places all channels into hold mode when high. Sets the polarity of the SELECT pin. +5V Logic Supply Digital GND -5V Analog Supply Analog GND Input Pin No connection. Not internally connected. Outputs 0-15 Pins +10V Analog Supply Outputs 16-31 Pins Bit 0 of the Address Decoder Bit 1 of the Address Decoder FUNCTION
MAX5168
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
ADDR0-ADDR4
S/H SELECT CONFIG CS SW1 SW2 SW30 SW31
MAX5168
OUT0
OUT1
IN
OUT30
OUT31
Figure 1. Functional Diagram
Detailed Description
Digital Interface
The MAX5168 has three logic control inputs and five address lines. The address lines are inputs to a demultiplexer that selects one of the 32 outputs in a standard addressing scheme (Table 1). The analog input is connected to the addressed sample/hold when directed by the control logic (Table 2). The three logic control lines determine the state of the addressed sample/hold. The normal circuit connection for this device is to hardwire CONFIG and SELECT to opposing logic voltages. When SELECT and CONFIG are in opposite states (one high and the other low), the five address lines select one of the sample/holds. Use the S/H line to place the selected channel into sample or hold mode. The other 31 channels will remain in hold mode. If an active-high sampling mode is desired, tie S/H and CONFIG low. In this case, SELECT controls the addressed channel with a high state putting that channel into sample mode.
6
The SELECT and CONFIG pins allow the design of a virtual 64-channel device using two of the MAX5168s. See the Applications Information section for more information about 64-plus output addressing schemes.
Sample/Hold
The MAX5168 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The value of the hold capacitor affects acquisition time and droop rate. Smaller capacitance allows faster acquisition times but increases the droop rate. Larger values increase hold acquisition time. The hold capacitor used in the MAX5168 provides fast 2.5s (typ) acquisition time while maintaining a relatively low 1mV/s (typ) droop rate, making the sample/hold ideal for highspeed sampling. Sample Mode When SELECT and CONFIG are in opposing logic states, the S/H line controls the mode of operation. Sample mode is entered when S/H is low. During sample mode, the
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
Table 1. Channel/Output Selection
ADDR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADDR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADDR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADDR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADDR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT24 VOUT25 VOUT26 VOUT27 VOUT28 VOUT29 VOUT30 VOUT31 OUTPUT SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED SELECTED
Table 2. Logic Table for CONFIG, SELECT, and S/H
S/H (SAMPLE/HOLD) 0 0 0 0 1 X = Don't care. _______________________________________________________________________________________ 7 CONFIG 0 0 1 1 X SELECT 0 1 0 1 X CHANNEL FUNCTION Hold Sampling Sampling Hold Hold
32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
selected multiplexer channel connects to IN, allowing the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for at least 4s. The output of the sample/hold amplifier tracks the input after 4s. Only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. Hold Mode No matter what the condition of the other control lines, S/H = high places the MAX5168 into an all-channel hold mode. Hold mode disables the multiplexer and disconnects all 32 sample/holds from the input. When a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a 1mV/s typical droop rate (towards VDD). Hold Step When switching between sample mode and hold mode, the voltage of the hold capacitor changes due to charge injection from stray capacitance. This voltage change, called a hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. The MAX5168 limits the hold step to 0.25mV (typ). An output capacitor to ground can be used to filter out this small hold-step error. when RL = , then AV = 1, and this equation becomes (VSS + 0.75V) VOUT (VDD - 2.4V)
Timing Definitions
Acquisition time (tAQ) is the time the MAX5168 must remain in sample mode for the hold capacitor to acquire an accurate sample. The hold-mode settling time (tH) is the time necessary for the output voltage to settle to its final value. Aperture delay (tAP) is the time interval required to disconnect the input from the hold capacitor. The hold pulse width (tPW) is the time the MAX5168 must remain in hold mode while the address is changed. Data setup time (t DS ) is the time an address must be maintained at the digital input pins before the address becomes valid. Data hold time (tDH) is the time an address must be maintained after the device is placed in hold mode (Figure 2).
Applications Information
Multiplexing a DAC
Figure 3 shows a typical demultiplexer application. Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on 32 different channels of the MAX5168. The 40mV/s (max) droop rate requires refreshing the hold capacitors every 250ms before the voltage droops by 1/2LSB for an 8-bit DAC with a 5V full-scale voltage.
Output
The MAX5168 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a high-impedance input that reduces the droop rate. The capacitor droops at 1mV/s (typ) while in hold mode. The buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output (Figure 1) for selected output filtering. To provide greater design flexibility, the MAX5168 is available with an output impedance of 50, 500, or 1k. Output loads increase the analog supply current (IDD and ISS). Excessive loading of the output(s) drastically increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute Maximum Ratings. The resistor-divider formed by the output resistor (RO) and load impedance (R L ) scales the sampled voltage (VSAMP). Determine the output voltage (VOUT_) as follows: Voltage Gain = AV = RL / (RL + RO) VOUT_ = VSAMP AV The maximum output voltage range depends on the analog supply voltages available and the scaling factor used: (VSS + 0.75V) AV VOUT_ (VDD - 2.4V) AV
Virtual 64 Output Sample/Hold
Two MAX5168s can be configured to operate as a single 64 output sample/hold. The upper and lower addressed devices are identified by CONFIG's logic level. Connect the CONFIG pin of the upper device low, making its SELECT pin active high. Connect the CONFIG pin of the lower device high to make the SELECT pin active low. Figure 4 shows how to configure the devices. The devices now use only six address lines and a single S/H control to decode 64 outputs. Address lines A0-A4 from the control logic connect to ADDR0- ADDR4 on both of the 32-channel devices. The A5 line toggles the SELECT pins of both devices to select the active one. The device that has CONFIG tied high responds to the lower 32 addresses (000000 through 011111). The device that has CONFIG grounded responds to the upper 32 addresses (100000 through 111111).
8
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
tPW S/H
tDH ADDR_ SELECT, CONFIG
tDS
tH OUT_
HOLD STEP
IN
tAQ
tAP
(CHANNEL x FROM HOLD TO SAMPLE)
(CHANNEL x FROM SAMPLE TO HOLD)
Figure 2. Timing Diagram
VL SELECT
ADDRESS BUS ADDR0-ADDR4 S/H
ADDRESS DECODER CS SWITCHES 0-31 OUT0
MAX5168
OUT1 IN
DATA BUS
DAC
OUT30
OUT31
CONFIG
Figure 3. Multiplexing a DAC
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
VL CONFIG A0-A4 A5 WR INPUT ADDR0-ADDR4 SELECT S/H IN OUT30 OUT31 OUT0 OUT1
MAX5168
OUT32 ADDR0-ADDR4 SELECT S/H IN CONFIG OUT62 OUT63 OUT33
MAX5168
Figure 4. 64-Output Sample/Hold Circuit
Input Drive Requirements
The input of the MAX5168 feeds the inputs of 32 highimpedance buffers. These buffers are what charge the sample/hold capacitor through the multiplexer switch resistance. The bias current of a selected buffer is 10A, and this feeds into the 10pF input capacitance. Figure 5 shows an equivalent input circuit. The bias currents of the other 31 sample and holds are very small in comparison to the bias current of the selected channel.
IBIAS 10A, INH = LOW
CIN 10pF
Powering the MAX5168
The MAX5168 does not require a special power-up sequence to avoid latchup. The device requires three separate supply voltages for operation. However, when one or two of the voltages are not available, DC-DC charge-pump (switched-capacitor) converters provide a simple, efficient solution. The MAX860 provides voltage doubling or inversion, ideal for conversions from +5V to +10V or from +5V to -5V.
Figure 5. Input Equivalent Circuit
Chip Information
TRANSISTOR COUNT: 6961
10
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
Package Information
32L/48L,TQFP.EPS
MAX5168
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32-Channel Sample/Hold Amplifier with a Single Multiplexed Input MAX5168
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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